Electrical & Computer Engineering · CMU

Cole Drake

RTL Design & Verification · Computer Architecture · CMU ECE

Electrical & Computer Engineering student at Carnegie Mellon University. I love computers! A CPU is a sports car, fast, but built for a specific job. A GPU is a school bus, great at moving lots of passengers at once. An FPGA is a junkyard full of parts, where you can build anything from a tricycle to an airplane. And that’s what excites me about hardware design: the ability to build something entirely new and make computers faster.

Pittsburgh, PA

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Education

Carnegie Mellon University

Pittsburgh, PA

B.S. Electrical & Computer Engineering, Minor in RoboticsExpected May 2027

Relevant coursework

Computer Systems
Computer Architecture
Structure and Design of Digital Systems
Logic Design and Verification

Skills

Languages

SystemVerilog
Verilog
C
C++
Python
Java
JavaScript
SQL

Hardware / Systems

RTL Design
Digital Design
FPGA
UVM
Testbench Development
SVA
Embedded Systems

Tools

Vivado
Quartus
Linux
Git
OpenCV
PyTorch
NVIDIA Jetson
MATLAB
ANSYS

Projects

May 2026 – Present

RISC-V Processor Microarchitecture

Verification & Design Project

SystemVerilog
RISC-V
Ibex
SVA
Functional Coverage

Extended the open-source Ibex RISC-V core with branch prediction, L1 instruction and data caches, and 14 new performance counter events, achieving a 3.06× speedup (IPC 0.150 → 0.457) across 11 workloads.

Designed ~2,300 lines of SystemVerilog RTL: 6 branch predictors (up to 94% accuracy) with a RAS and BTB, and parameterized set-associative caches with configurable replacement, write policy, and next-line prefetch.
Adapted the CV32E40P verification environment for Ibex with 4 checkers, 32 SVA assertions, and 100 coverage bins; automated a 776-simulation regression across 10 configurations with 100% coverage closure.
Ran 11 design-space studies (CPI, MPKI, miss rates) showing caches drove 2.9× vs. 5.5% from prediction; diagnosed a cache-conflict pathology fixed by 4-way associativity (2.6× on the affected workload).

The extended Ibex core: stock 2-stage pipeline in gray, my additions (branch predictor, L1 caches, performance counters) in teal.

November 2025

Pipelined Matrix-Vector Multiplier

Spartan-7 FPGA

SystemVerilog
Vivado
Spartan-7 FPGA

A pipelined multiply accumulate engine that computes a 128×128 matrix-vector product in 521 cycles, within 2% of the 512-cycle theoretical minimum.

Replicated operand ROMs across 36 dual-port BRAMs to feed 32 DSP multipliers in parallel (32 MACs/clock, ~99% of on-chip BRAM).
Met 100 MHz timing (+1.01 ns WNS) by registering each level of a 5-stage adder tree.
Overlapped the bias-vector reduction with the main datapath so it adds zero cycles.

Datapath and schedule: 32 products per clock through a registered 5-level adder tree, with the bias path hidden underneath.

Vivado simulation waveform of the first cycles of the multiply-accumulate pipeline.

April 2025 – April 2026

Hip Exoskeleton Control Validation

Metamobility Lab · Machine Learning Researcher

Python
NVIDIA Jetson
Sensor Fusion
Controls

Real-world validation of a hip exoskeleton control system integrating IMUs, motor encoders, and foot pressure sensors.

Led 150+ hours of real-world validation testing.
Analyzed multi-sensor data in Python to identify failure modes across 3 control model iterations deployed on NVIDIA Jetson.
Expanded the operating range from 1.0 m/s on flat ground to 0.4–1.4 m/s across ±12° inclines, reducing control error by ~90%.

September 2025 – Present

Multi-Camera 3D Scene Reconstruction

WiseLab · Hardware Research Intern

OpenCV
PyTorch
Python
Camera Calibration

A synchronized 4-camera capture system (1080p @ 60 FPS) and the pipeline that turns its footage into rendered 3D scenes.

Built the capture rig with OpenCV intrinsic/extrinsic calibration for multi-view alignment.
Developed the capture, synchronization, and preprocessing pipeline feeding 3D scene reconstruction.
Trained and tuned a PyTorch neural point-based graphics (NPBG) model, adding a point-sampling stage to reduce rendering compute.